Nano-fabrication includes the fabrication of very small structures that have features on the order of 100 nanometers or smaller. One application in which nano-fabrication has had a sizeable impact is in the processing of integrated circuits. The semiconductor processing industry continues to strive for larger production yields while increasing the circuits per unit area formed on a substrate; therefore nano-fabrication becomes increasingly important. Nano-fabrication provides greater process control while allowing continued reduction of the minimum feature dimensions of the structures formed.
An exemplary nano-fabrication technique in use today is commonly referred to as nanoimprint lithography. Nanoimprint lithography is useful in a variety of applications including, for example, fabricating layers of integrated devices such as CMOS logic, microprocessors, NAND Flash memory, NOR Flash memory, DRAM memory, or other memory devices such as MRAM, 3D cross-point memory, Re-RAM, Fe-RAM, STT-RAM, and the like. Exemplary nanoimprint lithography processes are described in detail in numerous publications, such as U.S. Pat. No. 8,349,241, U.S. Pat. No. 8,066,930, and U.S. Pat. No. 6,936,194, all of which are hereby incorporated by reference herein.
A nanoimprint lithography technique disclosed in each of the aforementioned U.S. patents includes formation of a relief pattern in a formable (polymerizable) layer and transferring a pattern corresponding to the relief pattern into an underlying substrate. The substrate may be coupled to a motion stage to obtain a desired positioning to facilitate the patterning process. The patterning process uses a template spaced apart from the substrate and a formable liquid applied between the template and the substrate. The formable liquid is solidified to form a rigid layer that has a pattern conforming to a shape of the surface of the template that contacts the formable liquid. After solidification, the template is separated from the rigid layer such that the template and the substrate are spaced apart. The substrate and the solidified layer are then subjected to additional processes to transfer a relief image into the substrate that corresponds to the pattern in the solidified layer.
An additional nanoimprint lithography technique involves forming a planarized layer over the previously solidified patterned layer and then subjecting the substrate, the solidified patterned layer, and the planarized layer to additional process to transfer a relief image into the substrate the corresponds to the inverse or reverse of the solidified layer pattern. Such processes have become increasingly important in nanoimprint lithography, as well as in other lithography processes, that are used in integrated device fabrication. However, difficulties in achieving adequate planarization of planarized layer while retaining adequate etch selectivity have limited the effectiveness of such processes, especially when pattern features with critical dimensions of 20 nm and below are required.